According to Reuters, Marco Pieters, Senior Vice President and Chief Technology Officer of ASML, disclosed key performance indicators at the meeting. The data shows that this model EXE: 520B High NA EUV equipment has processed over 500000 silicon wafers cumulatively.
Pieters pointed out that the stability performance of the device during testing exceeded expectations. At present, the utilization rate (Uptime) of this model has reached 80%. The official goal set by ASML is to further increase this number to 90% by the end of 2026, in order to fully meet the high standards of round the clock production required by top contract manufacturers worldwide.
For a long time, the manufacturing of chips below 2 nanometers has faced significant challenges in terms of process complexity. The core of High NA EUV technology is to increase the numerical aperture (NA) from 0.33 to 0.55.
Reuters reported citing ASML experts' analysis that the imaging accuracy demonstrated by the machine is sufficient to convince major customers to reduce the expensive and cumbersome "multiple exposure" steps. By using a 'single exposure', micro circuits that originally required multiple processes to print can be completed, which not only significantly improves production yield but also reduces costs in long-term production.

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